Complementary metal-oxide-semiconductor (CMOS) technology is used in microprocessors, static random access memories, and other diverse types of digital logic integrated circuits and analog integrated circuits. Conventional device structures for a planar field effect transistor (FET) fabricated using CMOS technology include a semiconductor layer, a source and a drain defined in the semiconductor layer, a channel defined in the semiconductor layer between the source and drain, and a control gate electrode. The material constituting the gate electrode in such conventional planar device structures contains polycrystalline silicon (polysilicon) or a metal applied by an additive process that involves blanket deposition of the material and patterning with a conventional lithography and etching process. When a control voltage exceeding a characteristic threshold voltage is applied to the control gate electrode, an depletion and then inversion layer is formed in the channel by the resultant electric field and carrier flow occurs in the inversion layer between the source and drain (i.e., the device output current).
In certain CMOS designs, low-voltage MOSFETs and high-voltage MOSFETs and junction field effect transistors (JFETs) are fabricated as a unitary integrated circuit. The former device type may be used for logic functions. The latter device type may be used for analog functions, such as radiofrequency switches and power amplifiers. This single chip implementation may be accomplished by reliance on thin gate oxide layers for the low-voltage MOSFETs and thicker gate oxide layers for high-voltage MOSFETs and JFETs. The thicker gate oxide layers are required because the high-voltage MOSFETs and JFETs operate at control voltages exceeding 10 volts, which is significantly higher than the low-voltage logic MOSFETs. Thick gate oxides may be difficult to perfect in high-performance CMOS because of the relatively small thickness of the SOI layer. Moreover, integration of both low-voltage MOSFET devices and high-voltage MOSFET or JFET devices in a single integrated circuit in conventional CMOS fabrication schemes may require a relatively large number of fabrication steps and a large number of different masks as the devices are concurrently fabricated.
Consequently, improved device structures and fabrication methods are needed for high voltage MOSFETs and JFETs that overcome these and other deficiencies of conventional device structures for high-voltage MOSFETs and JFETs and conventional fabrication methods.